ṉ FPGAϵyOӋм |
FPGAϵyOӋӖnҪWTM CPLD/FPGA _l̺OӋԹ̌`ѭuMČWFPGAļ_lh_lԼӲ·OӋ֪Rÿn̶PӖÿӖ}ĿCyclone(ZLϵ)FPGAӲƽ_MdCͨ^WTԸõn֪Ř`ˮƽõѸ |
nĿ |
BWTѸպʹCPLD/FPGAϵy_l_l܉MгFPGAϵyOӋ^ӖWTHDLZԵij_lҽQFPGAaƷ_l^еijҊ}ջFPGAOӋ{ԇ |
B |
FPGAϵyܛӲ_l̎IĴWоӮaƷOӋۺ |
WҪ |
WTWn̑߂лA֪R
·ϵyĻ |
༉Ҏģh |
˱CӖЧӻӭh҂ԳСnÿڈ˔35ˆTŵһMС |
nrg͵c |
ncϺͬW()/³ǽ̄(11̖y·վ) ڷֲӰB(Fһ̖Ժվ)/ڴWɽԺ ֲɽWԺ/δ Ͼֲ۴B(·) hֲԴB¶· ɶֲI^^1̖кʹ ꖷֲW/լƷ ݷֲݴW/\AB ʯfֲӱƼW/B
_nrg(ĩ/Bm/ࣩFPGAм_nrg2025714..ķ..........--_n--(_nՈԃͷ).... |
Wr |
nr Ոԃͷ
،WTʳޣǰA
ע|
߅v߅
ϸWTM]
ϸWTMClP̎YCIY|
ע߶Ӗ15ﺣṩCõИIďVJWT
õҵJͬܵˆλďVٝu
OՈc@鿴 |
|
Fwݴʩ95ۃ˻9ۃ ע⣺xW{WCʹһҲ500Ԫ
ͬrxFPGAOӋࡷ܃! |
| |
1Ӗ^вփⲻãMԺӖ
2ӖYMṩļgֱ֧CӖЧ
3ӖϸWTM]͘IC ϸWTMClP̎YCIY|ע߶Ӗ13꣬ﺣṩCõИIďVJɣWTõҵJͬܵˆλďVٝu |
YF |
wώ
FPGAn̽vĿdzS15FPGA/DSPϵyӲ_lϤEDAOӋ̣쾚ʹAlterXinlinx,ModelSim_lͨVerilog
HDLZԺVHDLZԣͨNios II EDS/SOPCIPPCI PLX 9054ɼ_l
ώ
YFPGA_l̎,FPGAӖn̽v8FPGADSPϵyӲ_l,4һֱҕl͈D̎IĸDSPϵyӲܛFPGAϵyOӋ_lзdzSĸϵyOӋͨTI˾C6000ϵиDSPAltera˾ȫϵFPGA/CPLD
YՈҊﺣYFꠣՈc@鿴 |
nMȰ |
n̴V̌WЃɷNZ汾WTWVHDLZԾ҂ɸҪ{ |
һA |
һAεnҪWT˽FPGAϵyOӋĻA֪RFPGAСϵyӲ·OӋWQuartusIIܛFPGAOӋ_l |
1.ɾ߉OӋg
2.һɾ߉OӋgչ
3.ɾ߉ӲϵĴlչڅ
4.EDAܛOӋlչڅ
5.FPGAOӋ
6.FPGAij_l
7.FPGAĻY
8.ͳɱFPGA Cyclone
9.һͳɱFPGA Cyclone II
10.FPGAоƬxͲԔ
11.FPGAPI·OӋС·OӋ
11.1 FPGA_OӋ
11.2 dc{ԇӿ·OӋ
11.3 RS-232
11.4 ַҺ@ʾӿ·OӋ
11.5 Դ·OӋ
11.6 λ·OӋ
11.7 ܴa_P·OӋ
11.8 i2c·OӋ
11.9 r·OӋ
11.10 DҺ·OӋ
12.Alter FPGAĽY
12.1 Alter ܶFPGA-StratixĽYȲ߉Ԫӿ
12.2 Alter ͳɱFPGA-Cyclone,Cyclone
II ĽYȲ߉Ԫӿ
12.3 Alter FPGAIJ
|
1. һAlteraFPGA_l\һӿڌ-ͨOӋFοRed,Green,Yellowϱ|Ľ\
Ӗn}ͨOӋF
Ҫc
1.1 Quartus IĪO
1.2 Quartus IIԴļOӋݔ뷽ʽ
1.3 Quartus IIsOӋ
1.4 Quartus II̾g
1.5 Quartus IIܷ
1.6 Quartus IIr
1.7 Quartus IIӲd |
ڶA |
쾚ӲZ(Verilog
HDL)FPGA̎ĻҪͨ^n̵ČWWT˽ĿǰеVerilog HDLZԵĻZVerilog
HDLZõĻZͨ^ňWWTOӋһЩεFPGAսM߉͕r߉·OӋͨ^ӖWTԌVerilog
HDLZиJR |
1.Verilog
HDLZԺ
2.Verilog HDLZ߉ϵy
3.Verilog HDLͲ
4.Verilog HDLVHDLZԵČ
5.Verilog HDLѭhZ
6.Verilog HDLĻY
7.Verilog HDLZԵĔͺ\
8.Verilog HDLZԵxֵZ͉KZͷxֵZą^e
9.Verilog HDLZԵėlZIFZCASEZĵ͑
10.Verilog HDLZԵZ
11.Verilog HDLZԌFM߉·
12.Verilog HDLZԌFr߉·
|
1. Ӗ
Ӗn}·xOӋ
Ҫc
1.1 Quartus IIܛ
1.2 M߉·OӋF
1.3 IFZCASEZʹ
2. Ӗ
Ӗn}ROӋF
Ҫc
2.1 Quartus IIܛ
2.2 r߉·OӋF
2.3 lԭ͌F
3. Ӗģ
Ӗn}Δaܜyԇ-ԄӑB跽ʽڣλaܡͬr@ʾ-
Ҫc
3.1 Quartus IIܛ
3.2 ˽ΰһl݆aܵCOMͳƽͬrͳĔo
3.3 Ba܄ӑB@ʾķ |
A |
mȻõڶAňWHDLZɴֵFPGAsFPGAϵyOӋ܉đVerilog
HDLĸZY_°빦Чͨ^n̵ČWWT΄գTASKFUNCTIONޠBCFSMOӋԸõFPGAOӋgn߀BQuartusIIܛăɂõĸߣSignalTAPFPGAOӋ{ԇЧ |
1.
TASKFUNCTIONZđÈ
2. Verilog HDLZY΄գTASK
3. Verilog HDLZY΄գFUNCTION
4. ޠBC(FSM)OӋԭaL
5. ߉CϵԭtԼɾCϵĴaOӋL
6. SignalTap IIھ߉xʹ÷
|
1. Ӗ壺
Ӗn}͠BCOӋ
Ҫc
1.1 FSMOӋ
1.2 BCľaBinarygray-codeone-hotȣ
1.3 BCijʼBĬJBBCOӋ
1.4 BCĠBxL
1.5 BCľL
2. Ӗ
Ӗn}ܴa_POӋ
Ҫc
2.1 Quartus IIݔ뷽ʽ
2.2 SignalTap IIھ{ԇ
2.3 ˽ܴa_PĹԭ·OӋ
3. Ӗߣ
Ӗn}IPOӋ
Ҫc
3.1 Quartus IIԭDݔ뷽ʽ
3.2 ˽IPĹԭ·OӋ
4. ӖˣSignalTap II߉x
4.1 SignalTap II߉x
4.2 SignalTap II߉xʹü
|
A |
SFPGAоƬܺܶȲ,
FPGASOPCϵyu첢ںܶIõˑAnҪoWTBAltera˾NIOSIIܛ˵SoPCϵyOӋ̺ͷͨ^Ӳ_lϵSoPCϵyOӋWT܉wSoPCgoϵyOӋ`ͨ^FPGACOӋWTɌWݵĻͿY |
1.
FPGAϵyMԭ͵ͷ
2. Altera˾ĽQ
3. FPGAľ˼ĿY
4. FPGAӲ_l˼·
5. FPGA{ԇ |
1. Ӗţ
Ӗn}惦xyԇ
Ҫc
2.1 FPGA{ԇ
2.2 FPGAܛ_l
2. Ӗʮ
Ӗn}FPGACOӋ
Ӗݣ ᘌһCԌ}ĿWTYOӋaOӋCͳd̻
Ҫc |
A |
1.Ӗʮһ
Ӗn}aMλcˢ¾COӋ
EһԔһ䁉|Ԍͨ^v┵aܸNMλķcMλaľע⣺
a.awˢº͔a܄ӑB@ʾą^eϵӾa
b.עFPGAľ裺\
c.עڂf^ʲô^
EWTԼһ֕r犳
a.ӖWTeһ
b.עһЩ÷
EYWTijeԭoQ
2.Ӗʮ
Ӗn}Qףӡ
EһԔһ䁉|Ԍͨ^vͨ^l팍FA{ע⣺
a.BCĸ÷
b.ӷl
c.עڂf^Уʲô^
EWTԼһ֕r犳
a.ӖWTeһ
b.עһЩ÷
EYWTijeԭoQ
3.Ӗʮ
1. ݵĻcycɴ
2.eһڅR؞ͨӖ
3. FPGAij̻ |
A |
֪RԔ⣺
1.ַҺ@ʾԭ
2.DҺ@ʾԭ
3.Һ@ʾԭԔ
4.I2Cfhԭc |
1. Ӗʮģ
Ӗn}1602ַҺ@ʾ
Ӗݣ ͨ^ַҺ@ʾԭͨ^awFᘌһCԌ}ĿWTYOӋaOӋ
2. Ӗʮ壺
Ӗn}128x64DҺ@ʾ
Ӗݣ ͨ^ֈDҺ@ʾԭͨ^awFᘌһCԌ}ĿWTYOӋaOӋ
. Ӗʮ
Ӗn}I2CxEEPROM
Ӗݣ ͨ^I2CfhԭI2CfhFEEPROMxʾͨ^awFᘌһCԌ}ĿWTYOӋaOӋ |